The subject matter of this application relates to computer systems, and more particularly, to a new implementation of buses and interface circuits which interface peripherals to storage controllers and main memory. This application describes a new implementation of a slower asynchronous first bus, a faster synchronous second bus, and an interface controller which interconnects and buffers the slower first bus to the faster second bus.
Computer systems include peripheral input output (I/0) equipment which must communicate with an instruction processing unit (IPU) and a main memory. This communication occurs via a bus, interconnecting the IPU and main memory to the peripheral equipment, for transmitting commands, instructions and data from the IPU/main memory to the peripherals and from the peripherals to the IPU/main memory. There are different types of buses. Some are faster, in their operation, than others. If a faster bus were to interface with a slower bus, the faster bus would overrun the slower bus. In addition, the needs of the IPU/main memory are different than the needs of the peripherals. Therefore, a second bus, for transmitting commands, instructions and data from and to the IPU/main memory, must be different than a first bus for transmitting commands, instructions and data from and to the peripherals. Consequently, a need exists for the first bus, for communication with the peripherals, the second bus, for communication with the IPU/main memory, and an interface circuit, interconnecting the two busses, for interfacing and buffering the first bus with the second bus.